In silicon gate MOS technology, optimal device characteristics are realized when the electrical channel length is equal to the length of the patterned gate. In other words, optimum performance occurs when the source/drain regions are precisely aligned to the gate edge. As a result, it is desirable to construct MOS transistors in a manner to assure source/drain alignment with the gate edge.
Methods for constructing MOS transistors in the current art include both the reach-through and push-through processes. For shorter channel devices (i.e., channel less than 2 .mu.m), push-through processing is typically used to contact the gate edge with the diffused regions. In this process, doping is done self-aligned to the gate sidewall spacers. The dopants are subsequently diffused during the source/drain anneal in order to reach the gate edge. The anneal time and temperature are critical because, ideally, the source/drain dopants should just reach the gate edge. If too little diffusion occurs, then the source/drain will fail to reach the gate edge, which, in turn, leads to increased source/drain series resistance and reduced drive current. Alternatively, if too much diffusion occurs, then there is overlap of the source/drain and gate edge which leads to increased gate-to-source/drain capacitance, and decreased effective electrical channel length. Smaller effective channel length increases short channel effects such as punch-through and hot electron degradation.
Another method currently used in an effort to align the source/drain regions with the gate edge is the reach-through lightly doped drain profile. Under this methodology, a light source/drain dose is implanted self-aligned to the gate edges. Thereafter, sidewall spacers are formed on the sides of the gate and the main source/drain regions are implanted. The lightly doped drain structure insures that there is no underlap between source/drain and the gate edge. However, this process does not solve the problem of too much diffusion which leads to overlap and the problems mentioned above.
Therefore, a need has arisen for a MOS transistor and the methodology of fabrication thereof which assures self-alignment between the source/drain regions and the gate edges of the transistor.